The size of semiconductor memory devices, and the thin dielectric films that comprise these devices, has been scaled down over the past years in order to fulfill the requirements of diminishing feature size. Further scaling down presents serious problems. One large problem, in floating gate memory devices, is that the charge retention characteristics of the devices are very sensitive to the presence or absence of defects in the tunnel oxide. A reduction in the thickness of the tunnel oxide, to allow for further scaling down, increases the risk of defects occurring in the tunnel oxide.
One partial solution to this problem is to store the charge in a floating gate comprised of a plurality of nanodots, instead of a monolithic floating gate. This plurality strongly reduces the sensitivity of the device to incidental defects in the tunnel oxide. In such a situation, when a defect is present, a nanodot immediately adjacent the defect might lose its charge but the other nanodots are not affected. See, e.g., U.S. Pat. No. 6,165,842 to Shin et al., issued Dec. 26, 2000; U.S. Pat. No. 5,714,766 to Chen et al., issued Feb. 3, 1998.
Nanodots made from silicon have been useful in making such gates. In recent years, a significant amount of research has been done in the area of silicon nanodots. Silicon nanodots are generally produced by low pressure chemical vapor deposition (LPCVD) and the process conditions can be readily optimized to produce silicon nanodots of a desired size and with a desired density. See, e.g., Baron et al., “Low pressure chemical vapor deposition growth of silicon quantum dots on insulators for nanoelectronic devices,” APPLIED SURFACE SCIENCE, Vol. 164, pp. 29–34 (2000).
More recently, one group has investigated the option of blended, or heterogeneous, silicon nitride nanodots. See, e.g., Koga et al., “Silicon Single-Electron Memory and Logic Devices For Room Temperature Operation,” IEDM 01–143, pp. 7.1.1–7.1.4 (2001). Silicon nitride nanodot devices show superior memory characteristics over silicon nanodot devices. Data retention characteristics are better and write characteristics show that a large memory window is attainable in each SiN dot device because multiple traps are formed in each SiN dot. Another advantage is that the silicon nitride dots are not as susceptible to oxidation. This can be important, for instance, in the case of a doubly stacked, floating dot memory device, where an upper dot is formed over a silicon layer. In the creation of such a device, the silicon layer is mostly oxidized, except for a lower silicon dot where the lower area is shielded from oxidation in a self-aligned manner by the upper dot. However, when the upper dot is formed of pure silicon, the upper dot will partially oxidize during the process and thus, size control of the lower dot is difficult. Using a silicon nitride dot as the upper dot largely eliminates this problem, as silicon nitride is very resistant to oxidation.
The current practice for the creation of these silicon nitride dots is to use low pressure chemical vapor deposition. However, the manufacturing of silicon nitride dots by low pressure chemical vapor deposition (LPCVD) has several disadvantages. First, the deposition temperature for the silicon nitride LPCVD process is significantly higher than the deposition temperature for the silicon process, resulting in higher consumption of the thermal budget of the wafer, which is undesired. Second, the LPCVD seed conditions that produce SiN nanodots of a desired size and density are largely unknown and still need to be explored. Finally, the visibility of silicon nitride nanodots on a silicon oxide film, either with scanning electron microscopy (SEM) or with transmission electron microscopy (TEM), is rather poor, as compared to the visibility of silicon nanodots, thus making the silicon nitride dots hard to examine.